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MC74VHCT374A Octal D-Type Flip-Flop with 3-State Output
The MC74VHCT374A is an advanced high speed CMOS octal flip-flop with 3-state output fabricated with silicon gate CMOS technology. It achieves high speed operation similar to equivalent Bipolar Schottky TTL while maintaining CMOS low power dissipation. This 8-bit D-type flip-flop is controlled by a clock input and an output enable input. When the output enable input is high, the eight outputs are in a high impedance state. The internal circuit is composed of three stages, including a buffer output which provides high noise immunity and stable output. The VHCT inputs are compatible with TTL levels. This device can be used as a level converter for interfacing 3.3 V to 5.0 V, because it has full 5.0 V CMOS level output swings. The VHCT374A input and output (when disabled) structures provide protection when voltages between 0 V and 5.5 V are applied, regardless of the supply voltage. These input and output structures help prevent device destruction caused by supply voltage-input/output voltage mismatch, battery backup, hot insertion, etc.
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MARKING DIAGRAMS
20 VHCT374A AWLYYWWG 1
1
SOIC-20WB SUFFIX DW CASE 751D
20 VHCT 374A ALYWG G 1
1
* * * * * * * * * * * *
High Speed: fmax = 140 MHz (Typ) at VCC = 5.0 V Low Power Dissipation: ICC = 4 mA (Max) at TA = 25C TTL-Compatible Inputs: VIL = 0.8 V; VIH = 2.0 V Power Down Protection Provided on Inputs and Outputs Balanced Propagation Delays Designed for 4.5 V to 5.5 V Operating Range Low Noise: VOLP = 1.6 V (Max) Pin and Function Compatible with Other Standard Logic Families Latchup Performance Exceeds 300 mA ESD Performance: Human Body Model > 2000 V; Machine Model > 200 V Chip Complexity: 276 FETs or 69 Equivalent Gates Pb-Free Packages are Available*
TSSOP-20 SUFFIX DT CASE 948E
20 SOEIAJ-20 SUFFIX M CASE 967 74VHCT374 AWLYWWG 1
1
A = Assembly Location WL, L = Wafer Lot YY, Y = Year WW, W = Work Week G or G = Pb-Free Package (Note: Microdot may be in either location)
FUNCTION TABLE
INPUTS OE L L L H CP D H L X X OUTPUT Q H L No Change Z
L, H, X
*For additional information on our Pb-Free strategy and soldering details, please download the ON Semiconductor Soldering and Mounting Techniques Reference Manual, SOLDERRM/D.
(c) Semiconductor Components Industries, LLC, 2006
ORDERING INFORMATION
See detailed ordering and shipping information in the package dimensions section on page 4 of this data sheet.
1
January, 2006 - Rev. 4
Publication Order Number: MC74VHCT374A/D
MC74VHCT374A
3 D0 4 D1 7 D2 8 D3 13 D4 14 D5 17 D6 18 D7 11 CP OE 1 2 5 6 9 12 15 16 19 OE Q0 D0 NONINVERTING OUTPUTS D1 Q1 Q2 D2 D3 Q3 GND 1 2 3 4 5 6 7 8 9 10 20 19 18 17 16 15 14 13 12 11 VCC Q7 D7 D6 Q6 Q5 D5 D4 Q4 CP
DATA INPUTS
Q0 Q1 Q2 Q3 Q4 Q5 Q6 Q7
Figure 1. Logic Diagram
Figure 2. Pin Assignment
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MAXIMUM RATINGS
Symbol VCC Vin Parameter Value Unit V V V DC Supply Voltage DC Input Voltage - 0.5 to + 7.0 - 0.5 to + 7.0 Vout IIK DC Output Voltage Outputs in 3-State High or Low State - 0.5 to + 7.0 - 0.5 to VCC + 0.5 - 20 20 25 75 500 450 Input Diode Current mA mA mA mA IOK Iout Output Diode Current (VOUT < GND; VOUT > VCC) DC Output Current, per Pin ICC PD DC Supply Current, VCC and GND Pins Power Dissipation in Still Air, Storage Temperature SOIC Package TSSOP Package mW _C Tstg - 65 to + 150 Maximum ratings are those values beyond which device damage can occur. Maximum ratings applied to the device are individual stress limit values (not normal operating conditions) and are not valid simultaneously. If these limits are exceeded, device functional operation is not implied, damage may occur and reliability may be affected. Derating - SOIC Packages: - 7 mW/_C from 65_ to 125_C TSSOP Package: - 6.1 mW/_C from 65_ to 125_C
This device contains protection circuitry to guard against damage due to high static voltages or electric fields. However, precautions must be taken to avoid applications of any voltage higher than maximum rated voltages to this high-impedance circuit. For proper operation, Vin and Vout should be constrained to the range GND v (Vin or Vout) v VCC. Unused inputs must always be tied to an appropriate logic voltage level (e.g., either GND or V CC ). Unused outputs must be left open.
RECOMMENDED OPERATING CONDITIONS
Symbol VCC Vin Parameter Min 4.5 0 0 0 Max 5.5 5.5 Unit V V V DC Supply Voltage DC Input Voltage
Vout TA
DC Output Voltage
Outputs in 3-State High or Low State
5.5 VCC
Operating Temperature
- 40 0
+ 85 20
_C
tr, tf
Input Rise and Fall Time
VCC =5.0V 0.5V
ns/V
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MC74VHCT374A
I I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII I IIIII I I II I I I I I I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII I IIIII I II I I I I I I IIIII I I I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII I IIIII I IIIII I I I I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII I IIIII I IIIII I I I I I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII I I I I II I I I I I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII I III I III I I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII I IIIII II I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII I IIIII III I I II IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII I I I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII I IIIII I I I II I I I I I I II I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII IIIIII I I I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII I IIIII I I I II IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII I IIIIIII I I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII I IIIII I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII I IIIII I II I I I I I I II I I I I I I II I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII I I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII I IIIII I II I I I I I I IIIII I I I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII I IIIII I I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII I IIIII I I I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII I IIIII I I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII I IIIII I I II I I I I I I III I I I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII IIIIIIIIIIIIIIIIIIIII I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII I IIIII I IIII II I I I I I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII I IIIII I IIIII I I I I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII I I I II I I I I I I IIIII I IIIIIIIIIIIIIIIIIIIIII IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII I IIIII IIIIIIIIIIIIIIIIIIIII III I I IIII IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII IIIIIIIIIIII I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII IIIIIIIIIIII I IIIII I IIIII IIIII II I I I I I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII I IIIII I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII I I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII I I I I I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII
DC ELECTRICAL CHARACTERISTICS
Symbol VIH VIL VOH VOL Iin Parameter Minimum High-Level Input Voltage Minimum High-Level Output Voltage Vin = VIH or VIL Maximum Low-Level Output Voltage Vin = VIH or VIL Test Conditions VCC V TA = 25C Typ TA = - 40 to 85C Min 2.0 4.4 Max 0.8 Min 2.0 4.4 Max 0.8 4.5 to 5.5 4.5 to 5.5 4.5 4.5 4.5 4.5 5.5 5.5 5.5 0 Unit V V V V Maximum Low-Level Input Voltage IOH = - 50mA IOH = - 8mA IOL = 50mA IOL = 8mA 4.5 0.0 3.94 3.80 0.1 0.1 0.36 0.44 Maximum Input Leakage Current Vin = 5.5 V or GND Vin = VIL or VIH Vout = VCC or GND Vin = VCC or GND 0 to 5.5 0.1 1.0 mA mA mA IOZ Maximum 3-State Leakage Current 0.25 4.0 2.5 40.0 1.50 5.0 ICC Maximum Quiescent Supply Current Quiescent Supply Current Output Leakage Current ICCT Per Input: VIN = 3.4V Other Input: VCC or GND VOUT = 5.5V 1.35 0.5 mA mA IOPD
AC ELECTRICAL CHARACTERISTICS (Input tr = tf = 3.0ns)
Symbol fmax tPLH, tPHL tPZL, tPZH tPLZ, tPHZ Parameter Maximum Clock Frequency (50% Duty Cycle)
TA = 25C Typ 140 130 4.1 5.6 6.5 7.3 7.0
TA = - 40 to 85C Min 80 95 Max
Test Conditions VCC = 5.0 0.5V CL = 15pF CL = 50pF VCC = 5.0 0.5V CL = 15pF CL = 50pF
Min 90 85
Max
Unit MHz ns ns ns ns
Maximum Propagation Delay, CP to Q Output Enable Time, OE to Q Output Disable Time OE to Q
9.4 10.4 10.2 11.2 11.2 1.0 10
1.0 1.0 1.0 1.0 1.0
10.5 11.5
VCC = 5.0 0.5V CL = 15pF RL = 1kW CL = 50pF VCC = 5.0 0.5V RL = 1kW VCC = 5.0 0.5V (Note 1) CL = 50pF CL = 50pF
11.5 12.5
12.0 1.0 10
tOSLH, tOSHL Cin Cout
Output to Output Skew
Maximum Input Capacitance
4 9
pF pF
Maximum 3-State Output Capacitance (Output in High-Impedance State)
Typical @ 25C, VCC = 5.0V
25 CPD Power Dissipation Capacitance (Note 2) pF 1. Parameter guaranteed by design. tOSLH = |tPLHm - tPLHn|, tOSHL = |tPHLm - tPHLn|. 2. CPD is defined as the value of the internal equivalent capacitance which is calculated from the operating current consumption without load. Average operating current can be obtained by the equation: ICC(OPR) = CPD VCC fin + ICC / 8 (per flip-flop). CPD is used to determine the no-load dynamic power consumption; PD = CPD VCC2 fin + ICC VCC.
NOISE CHARACTERISTICS (Input tr = tf = 3.0ns, CL = 50pF, VCC = 5.0V)
TA = 25C Symbol VOLP VOLV VIHD VILD Parameter Quiet Output Maximum Dynamic VOL Quiet Output Minimum Dynamic VOL Minimum High Level Dynamic Input Voltage Maximum Low Level Dynamic Input Voltage Typ 1.2 -1.2 Max 1.6 -1.6 2.0 0.8 Unit V V V V
TIMING REQUIREMENTS (Input tr = tf = 3.0ns)
TA = 25C Symbol tw tsu th Parameter Minimum Pulse Width, CP Minimum Setup Time, D to CP Minimum Hold Time, D to CP Test Conditions VCC = 5.0 0.5 V VCC = 5.0 0.5 V VCC = 5.0 0.5 V Typ Limit 6.5 2.5 2.5 TA = - 40 to 85C Limit 8.5 2.5 2.5 Unit ns ns ns
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MC74VHCT374A
ORDERING INFORMATION
Device MC74VHCT374ADWR2 MC74VHCT374ADWRG MC74VHCT374ADTR2 MC74VHCT374ADTRG MC74VHCT374AMEL MC74VHCT374AMELG Package SOIC-20WB SOIC-20WB (Pb-Free) TSSOP-20* TSSOP-20* SOEIAJ-20 SOEIAJ-20 (Pb-Free) Shipping 1000 / Tape & Reel 1000 / Tape & Reel 2500 / Tape & Reel 2500 / Tape & Reel 2000 / Tape & Reel 2000 / Tape & Reel
For information on tape and reel specifications, including part orientation and tape sizes, please refer to our Tape and Reel Packaging Specifications Brochure, BRD8011/D. *This package is inherently Pb-Free.
3V CP 1.5V tW tPLH Q 1.5V VOL GND 1/fmax tPHL VOH
Figure 3. Switching Waveform
OE
3V 1.5V GND tPZL tPLZ HIGH IMPEDANCE VOL +0.3V tPZH tPHZ VOH -0.3V HIGH IMPEDANCE
Q
1.5V
Q
1.5V
Figure 4. Switching Waveform
VALID D 1.5V
3V GND
tsu CP 1.5V
th 3V GND
Figure 5. Switching Waveform
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MC74VHCT374A
TEST POINT OUTPUT DEVICE UNDER TEST C L*
*Includes all probe and jig capacitance
Figure 6. Test Circuit
TEST POINT OUTPUT DEVICE UNDER TEST 1 kW CONNECT TO VCC WHEN TESTING tPLZ AND tPZL. CONNECT TO GND WHEN TESTING tPHZ AND tPZH.
C L*
*Includes all probe and jig capacitance
Figure 7. Test Circuit
D0 3 D C CP OE 11 1 Q
D1 4 D C Q
D2 7 D C Q
D3 8 D C Q
D4 13 D C Q
D5 14 D C Q
D6 17 D C Q
D7 18 D C Q
2 Q0
5 Q1
6 Q2
9 Q3
12 Q4
15 Q5
16 Q6
19 Q7
Figure 8. Expanded Logic Diagram
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MC74VHCT374A
PACKAGE DIMENSIONS
SOIC-20 WB DW SUFFIX CASE 751D-05 ISSUE G
D
NOTES: 1. DIMENSIONS ARE IN MILLIMETERS. 2. INTERPRET DIMENSIONS AND TOLERANCES PER ASME Y14.5M, 1994. 3. DIMENSIONS D AND E DO NOT INCLUDE MOLD PROTRUSION. 4. MAXIMUM MOLD PROTRUSION 0.15 PER SIDE. 5. DIMENSION B DOES NOT INCLUDE DAMBAR PROTRUSION. ALLOWABLE PROTRUSION SHALL BE 0.13 TOTAL IN EXCESS OF B DIMENSION AT MAXIMUM MATERIAL CONDITION. DIM A A1 B C D E e H h L q MILLIMETERS MIN MAX 2.35 2.65 0.10 0.25 0.35 0.49 0.23 0.32 12.65 12.95 7.40 7.60 1.27 BSC 10.05 10.55 0.25 0.75 0.50 0.90 0_ 7_
A
11 X 45 _
q
H
M
B
M
20
10X
0.25
E
1
10
20X
B 0.25
M
B TA
S
B
S
A
SEATING PLANE
h
18X
e
A1
T
C
TSSOP-20 D5 SUFFIX CASE 948E-02 ISSUE B
20X
L
K REF
M
0.15 (0.006) T U
S
0.10 (0.004)
TU
S
V
S
B L
PIN 1 IDENT 1 10
J J1
-U-
N 0.15 (0.006) T U
S
A -V- N F
C D 0.100 (0.004) -T- SEATING
PLANE
G
H
DETAIL E
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IIII IIII IIII
SECTION N-N M DETAIL E
2X
L/2
20
11
K K1
0.25 (0.010)
NOTES: 1. DIMENSIONING AND TOLERANCING PER ANSI Y14.5M, 1982. 2. CONTROLLING DIMENSION: MILLIMETER. 3. DIMENSION A DOES NOT INCLUDE MOLD FLASH, PROTRUSIONS OR GATE BURRS. MOLD FLASH OR GATE BURRS SHALL NOT EXCEED 0.15 (0.006) PER SIDE. 4. DIMENSION B DOES NOT INCLUDE INTERLEAD FLASH OR PROTRUSION. INTERLEAD FLASH OR PROTRUSION SHALL NOT EXCEED 0.25 (0.010) PER SIDE. 5. DIMENSION K DOES NOT INCLUDE DAMBAR PROTRUSION. ALLOWABLE DAMBAR PROTRUSION SHALL BE 0.08 (0.003) TOTAL IN EXCESS OF THE K DIMENSION AT MAXIMUM MATERIAL CONDITION. 6. TERMINAL NUMBERS ARE SHOWN FOR REFERENCE ONLY. 7. DIMENSION A AND B ARE TO BE DETERMINED AT DATUM PLANE -W-. MILLIMETERS MIN MAX 6.40 6.60 4.30 4.50 --- 1.20 0.05 0.15 0.50 0.75 0.65 BSC 0.27 0.37 0.09 0.20 0.09 0.16 0.19 0.30 0.19 0.25 6.40 BSC 0_ 8_ INCHES MIN MAX 0.252 0.260 0.169 0.177 --- 0.047 0.002 0.006 0.020 0.030 0.026 BSC 0.011 0.015 0.004 0.008 0.004 0.006 0.007 0.012 0.007 0.010 0.252 BSC 0_ 8_
-W-
DIM A B C D F G H J J1 K K1 L M
MC74VHCT374A
PACKAGE DIMENSIONS
SOEIAJ-20 M SUFFIX CASE 967-01 ISSUE A
20
11
LE Q1 M_ L DETAIL P
E HE
1
10
Z D e VIEW P A
c
NOTES: 1. DIMENSIONING AND TOLERANCING PER ANSI Y14.5M, 1982. 2. CONTROLLING DIMENSION: MILLIMETER. 3. DIMENSIONS D AND E DO NOT INCLUDE MOLD FLASH OR PROTRUSIONS AND ARE MEASURED AT THE PARTING LINE. MOLD FLASH OR PROTRUSIONS SHALL NOT EXCEED 0.15 (0.006) PER SIDE. 4. TERMINAL NUMBERS ARE SHOWN FOR REFERENCE ONLY. 5. THE LEAD WIDTH DIMENSION (b) DOES NOT INCLUDE DAMBAR PROTRUSION. ALLOWABLE DAMBAR PROTRUSION SHALL BE 0.08 (0.003) TOTAL IN EXCESS OF THE LEAD WIDTH DIMENSION AT MAXIMUM MATERIAL CONDITION. DAMBAR CANNOT BE LOCATED ON THE LOWER RADIUS OR THE FOOT. MINIMUM SPACE BETWEEN PROTRUSIONS AND ADJACENT LEAD TO BE 0.46 ( 0.018). DIM A A1 b c D E e HE L LE M Q1 Z MILLIMETERS MIN MAX --- 2.05 0.05 0.20 0.35 0.50 0.15 0.25 12.35 12.80 5.10 5.45 1.27 BSC 7.40 8.20 0.50 0.85 1.10 1.50 10 _ 0_ 0.70 0.90 --- 0.81 INCHES MIN MAX --- 0.081 0.002 0.008 0.014 0.020 0.006 0.010 0.486 0.504 0.201 0.215 0.050 BSC 0.291 0.323 0.020 0.033 0.043 0.059 10 _ 0_ 0.028 0.035 --- 0.032
b 0.13 (0.005)
M
A1 0.10 (0.004)
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PUBLICATION ORDERING INFORMATION
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MC74VHCT374A/D

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